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 STL80NF3LL
N-CHANNEL 30V - 0.0045 - 80A PowerFLATTM ( 6X5 ) STripFETTM II MOSFET
PRODUCT PREVIEW
Table 1: General Features
TYPE STL80NF3LL

Figure 1: Package
RDS(on) < 0.0055 ID 20 A (2)
VDSS 30 V
TYPICAL RDS(on) = 0.0045 @ 10V IMPROVED DIE-TO-FOOTPRINT RATIO VERY LOW PROFILE PACKAGE (1mm MAX) VERY LOW THERMAL RESISTANCE CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED PowerFLATTM( 6x5 )
DESCRIPTION The STL80NF3LL utilizes the second generation of STMicroelectronics unique "Single Feature SizeTM" strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. Such features make it the best choice in high efficiency DC-DC converters for Telecom and Computer industries. The Chipscaled PowerFLATTM package allows a significant board space saving, still boosting the performance.
Figure 2: Internal Schematic Diagram
APPLICATIONS HIGH-EFFICIENCY DC-DC CONVERTERS SYNCHRONOUS RECTIFICATION
TOP VIEW
Table 2: Order Codes
Part Number STL80NF3LL Marking L80NF3LL Package PowerFLATTM (6x5) Packaging TAPE & REEL
Rev. 3 June 2005
This is a preliminary information on a new product now in development. Details are subjet to change without notice
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Table 3: Absolute Maximum ratings
Symbol VDS VGS ID (1) ID (1) IDM (3) ID (2) PTOT (2) PTOT (1) Tstg Tj Parameter Drain-source Voltage (VGS= 0) Gate- source Voltage Drain Current (continuous) at TC= 25C Drain Current (continuous) at TC= 100C Drain Current (pulsed) Drain Current (continuous) at TC= 25C Total Dissipation at TC= 25C Total Dissipation at TC= 25C Derating Factor(2) Storage Temperature Max. Operating Junction Temperature Value 30 16 80 50 320 20 4 80 0.03 - 55 to 150 Unit V V A A A A W W W/C C
Table 4: Thermal Data
Rthj-C Rthj-pcb (2) Thermal Resistance Junction-Case (Drain) Thermal Operating Junction-pcb 1.56 31.3 C/W C/W
ELECTRICAL CHARACTERISTICS (TCASE =25C UNLESS OTHERWISE SPECIFIED) Table 5: On /Off
Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125C VGS = 16 V VDS= VGS, ID= 250A VGS= 10 V, ID= 10 A VGS= 4.5 V, ID= 10 A 1 0.0045 0.0055 0.0055 0.007 Min. 30 1 10 10 Typ. Max. Unit V A A nA V
Table 6: Dynamic
Symbol gfs (4) Ciss Coss Crss RG Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Input Resistance f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain Test Conditions VDS= 10V, ID= 10 A VDS= 25V, f= 1 MHz, VGS= 0 Min. Typ. 37 2160 614 98 4.1 Max. Unit S pF pF pF
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ELECTRICAL CHARACTERISTICS (CONTINUED) Table 7: Switching On
Symbol td(on) tr td(off) tf Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Turn-off-Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD= 15 V, ID= 10 A RG = 4.7, VGS = 4.5V (see Figure 15) Min. Typ. 23.5 39 47.5 37 26 7 12 35 Max. Unit ns ns ns ns nC nC nC
VDD= 15V, ID= 10 A, VGS= 4.5 V (see Figure 17)
Table 8: Source Drain Diode
Symbol ISD ISDM (3) VSD (4) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse RecoveryCharge Reverse Recovery Current ISD= 20 A, VGS= 0 ISD= 20 A, di/dt= 100 A/s, VDD= 15 V, Tj = 150C (see Figure 16) 39 45 2.3 Test Conditions Min. Typ. Max. 20 80 1.3 Unit A A V ns nC A
(1) The value is rated according Rthj-C . (2) When mounted on FR-4 board of 1in, 2oz Cu., t<10sec (3) Pulse width limited by safe operating area. (4) Pulsed: Pulse duration = 300 s, duty cycle 1.5 %
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Figure 3: Safe Operating Area Figure 6: Thermal Impedance
Figure 4: Output Characteristics
Figure 7: Transfer Characteristics
Figure 5: Transconductance
Figure 8: Static Drain-source On Resistance
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Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations
Figure 10: Normalized Gate Thereshold Voltage vs Temperature
Figure 13: Normalized BVDSS vs Temperature
Figure 11: Normalized On Resistance vs Temperature
Figure 14: Source-Drain Diode Forward Characteristics
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Figure 15: Switching Times Test Circuit For Resistive Load Figure 17: Gate Charge Test Circuit
Figure 16: Test Circuit For Diode Recovery Times
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PowerFLATTM (6x5) MECHANICAL DATA
mm. DIM. MIN. A A1 A3 b D D1 D2 E E1 E2 E4 e L 0.70 3.43 2.58 4.15 0.35 0.80 TYP 0.83 0.02 0.20 0.40 5.00 4.75 4.20 6.00 5.75 3.48 2.63 1.27 0.80 0.90 0.027 3.53 2.68 0.135 4.25 0.163 0.47 0.013 MAX. 0.93 0.05 MIN. 0.031 TYP. 0.032 0.0007 0.007 0.015 0.196 0.187 0.165 0.236 0.226 0.137 0.103 0.050 0.031 0.035 0.139 0.105 0.167 0.018 MAX. 0.036 0.0019 inch
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Table 9: Revision History
Date 18-Apr-2005 20-Jun-2005 22-Jun-2005 Revision 1 2 3 Description of Changes First Release. Updated mechanical data New RG value on table 6
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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